In preparing monolithically integrated semiconductor components (also referred to as chips) distinct advantages have been recognized to result from employing monocrystalline semiconductive substrates presenting planar surfaces--i.e., surfaces having the low levels of relief common to semiconductor devices fabricated using planar processing. Planar surfaces exhibit a relief variance of a micrometer (.mu.m) or less.
When monocrystalline semiconductive substrates exhibit surface relief in excess of about 1 .mu.m, particularly when these relief differences are exhibited by next adjacent chip components, manufacturing difficulties arise leading to reduced yields. As the relief differences between adjacent chip elements increases, the slope of connecting surfaces of the substrate increases, shifting from a horizontal orientation toward a vertical orientation. As surface orientations become increasingly sloped, the choice of techniques by which overlying layers, such as insulative or conductive layers, can be deposited reliably is reduced. Additionally, increased relief differences impose localized reduced radii of curvature on overlying layers. It is at these sites in overlying layers that coating non-uniformities are most common. Further, it is at the low radius of curvature layer locations that stress defects, such as those attributable to differences in thermal expansion characteristics, are most likely to occur.
Botez, "Laser Diodes are Power-Packed", IEEE Spectrum, June 1985, pp. 43-53, provides a state of the art survey of laser diodes as discrete elements. Positive index lasers are disclosed and schematically illustrated.
Although it is a simple matter of Botez to show schmatically planar surfaces for discrete lasers, it has been a problem of long standing in the laser art to find ways of monolithically integrating lasers with other circuit components while achieving workable chip topographies. It is known in the art that a laser can be formed by planar processing. Such lasers are formed by introducing along a substrate surface N and P conductivity type ions in laterally spaced regions so that an active region is created therebetween. While such lasers are ideal in terms of achieving an overall planar surface for a chip, emission efficiency of such lasers is relatively low.
For this reason Botez limits discussion to lasers which consist of a plurality of superimposed semiconductive layers. Lasers can be formed with only three superimposed layers, superimposed N and P conductivity type layers with an active layer intervening. Efficient lasers are typically formed with five or more superimposed layers.
Perhaps the most common approach for preparing a monolithic circuit including a laser is to grow the required laser layers over the entire upper surface of the semiconductive substrate and then to remove these layers by etching from all but the desired laser areas. This produces lasers of the mesa type, with several layers protruding above the lowest common substrate surface. Attempts to overcome the high relief of mesa construction have included subsequently regrowing the substrate epitaxially in etched substrate regions. Unfortunately, this also results in additional deposits on the laser mesa so that ultimately achieving a surface that approaches a planar surface is a laborious undertaking and not readily achieved.
As a result of these difficulties one approach to which the art has resorted in monolithically integrating lasers and other semiconductive circuit components is to increase the lateral distance between the laser and next adjacent component spacing. While this does not reduce the relief difference between the laser surface and the adjacent component surface, it does reduce the slope of the intervening surfaces. Typical integrated circuit arrangements of this type are illustrated by Sanada et al, "Monolithic Integration of a Low Thresold Current Quantum Well Laser and a Driver Circuit on a GaAs Substrate," App. Phys. Lett. 46(3), Feb. 1, 1985, pp. 226-228, and Cohen, "Opto-electronic Chip Integrates Laser and Pair of FETs", Electronics, June 30, 1983, pp. 89 and 90. The inherent disadvantage of increased spacing to achieve reduced slope is that it is incompatible with the higher packing densities of chip components desired for efficient substrate utilization and therefore limits the number of elements which can be accomodated within a given chip area.
Recognizing the difficulties of integrating waveguides such as lasers in multicomponent chips, the art has continued to investigate the properties of waveguide semiconductive materials and the manner in which such materials can be deposited. Ghosh et al, "Selective Area Growth of Gallium Arsenide by Metalorganic Vapor Phase Epitaxy," App. Phys. Lett. 45(11), Dec. 1, 1984, pp. 1229-1231, discloses the selective growth of gallium arsenide by organometallic vapor phase epitaxy on a gallium arsenide substrate partially masked by a silica layer. Tokumitsu et al, "Molecular Beam Epitaxial Growth of GaAs Using Trimethylgallium as a Ga Source," J. App. Phys. 55(8), Apr. 15, 1984, pp. 3163-3165, reports similar selective deposition employing molecular beam epitaxy. Kamon et al, "Selective Epitaxial Growth of GaAs by Low Pressure MOVPE," Journal of Crystal Growth 73 (1985), pp. 73-76, discloses the selective growth of gallium arsenide on gallium arsenide in areas not covered by silica and in "Selective Embedded Growth of AlGaAs by Low-Pressure Organometallic Vapor Phase Epitaxy", Japanese Journal of Applied Physics, 25(1), Jan. 1, 1986, pp. L10-L12, extend their previous disclosure to growing selective gallium aluminum arsenide on an etched substrate.